PCIMX258CJM4A datasheet(67/144 Pages) FREESCALE

67 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

3.7.6.2

NAND Flash Controller (NFC) Timing

The i.MX25 NFC supports normal timing mode, using two Flash clock cycles for one access of RE and

WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 34 through

Figure 37 depicts the relative timing between NFC signals at the module level for different operations

under normal mode. Table 53 describes the timing parameters (NF1–NF17) that are shown in the figures.

Figure 34. Command Latch Cycle Timing Diagram

Figure 35. Address Latch Cycle Timing Diagram

2 SDRAM CLK and DQS-related parameters are measured from the 50% point. That is, high is defined as 50% of the signal

value, and low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of

SDCLK and SDCLK (inverted clock).

3 The value was calculated for an SDCLK frequency of 133 MHz, by the formula tQH = tHP – tQHS = min. (tCL,tCH) – tQHS =

0.45*tCK – tQHS = 0.45 * 7.5 – 0.45 = 2.925 ns

NFCLE

NFCE

NFWE

NFALE

NFIO[7:0]

Command

NF9

NF8

NF1

NF2

NF5

NF3

NF4

NF6

NF7

NFCLE

NFCE

NFWE

NFALE

NFIO[7:0]

Address

NF9

NF8

NF1

NF5

NF3

NF4

NF6

NF11

NF10

NF7

PCIMX258CJM4A Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc

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