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PCIMX258CJM4A Datasheet(PDF) 63 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 63 Page - Freescale Semiconductor, Inc |
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63 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 63 Figure 31. DDR2 SDRAM Basic Timing Parameters Table 48 provides values for a command/address slew rate of 1 V/ns and an SDCLK, SDCLK_B differential slew rate of 2 V/ns. For additional values, use Table 49, “tlS, tlH Derating Values for DDR2-400, DDR2-533.” Table 48. DDR2 SDRAM Timing Parameter Table ID Parameter Symbol DDR2-400 Unit Min. Max. DDR1 SDRAM clock high-level width tCH 0.45 0.55 tCK DDR2 SDRAM clock low-level width tCL 0.45 0.55 tCK DDR3 SDRAM clock cycle time tCK 7.5 8 ns DDR4 CS, RAS, CAS, CKE, WE setup time tIS 0.35 — ns DDR5 CS, RAS, CAS, CKE, WE hold time tIH 0.475 — ns DDR6 Address output setup time tIS 0.35 — ns DDR7 Address output hold time tIH 0.475 — ns SDCLK WE ADDR ROW/BA COL/BA CS CAS RAS DDR1 DDR3 DDR2 DDR4 DDR4 DDR4 DDR5 DDR5 DDR5 DDR5 DDR6 DDR7 SDCLK CKE DDR4 DDR4 |
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