PCIMX258CJM4A datasheet(87/144 Pages) FREESCALE

87 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

1 FEC_COL has the same timing in 10-Mbit 7-wire interface mode.

3.7.9.2

MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3

standard MII specification. However the FEC can function correctly with a maximum MDC frequency of

15 MHz.

Figure 58 shows MII asynchronous input timings. Table 63 describes the timing parameters

(M10—M15) shown in the figure.

Figure 58. MII Serial Management Channel Timing Diagram

Table 62. MII Asynchronous Inputs Signal Timing

Characteristic

Min.

Max.

Unit

M91

FEC_CRS to FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

Table 63. MII Serial Management Channel Timing

Characteristic

Min.

Max.

Unit

M10

FEC_MDC falling edge to FEC_MDIO output invalid (min.

propagation delay)

0—

M11

FEC_MDC falling edge to FEC_MDIO output valid (max.

propagation delay)

—5

M12

FEC_MDIO (input) to FEC_MDC rising edge setup

—

M13

FEC_MDIO (input) to FEC_MDC rising edge hold

—

M14

FEC_MDC pulse width high

40%

60%

FEC_MDC period

M15

FEC_MDC pulse width low

40%

60%

FEC_MDC period

FEC_MDC (output)

FEC_MDIO (output)

M14

M15

M10

M11

M12

M13

FEC_MDIO (input)

PCIMX258CJM4A Datasheet(PDF) 87 Page - Freescale Semiconductor, Inc

PCIMX258CJM4A Datasheet(HTML) 87 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL