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PCIMX258CJM4A Datasheet(PDF) 88 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 88 Page - Freescale Semiconductor, Inc |
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88 / 144 page ![]() i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 88 Freescale Semiconductor 3.7.9.3 RMII Mode Timing In RMII mode, FEC_TX_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock. FEC_RX_DV is used as the CRS_DV in RMII. Other signals under RMII mode include FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and FEC_RX_ER. Figure 59 shows RMII mode timings. Table 64 describes the timing parameters (M16–M21) shown in the figure. Figure 59. RMII Mode Signal Timing Diagram Table 64. RMII Signal Timing ID Characteristic Min. Max. Unit M16 REF_CLK(FEC_TX_CLK) pulse width high 35% 65% REF_CLK period M17 REF_CLK(FEC_TX_CLK) pulse width low 35% 65% REF_CLK period M18 REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid 3 — ns M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid — 12 ns M20 FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to REF_CLK setup 2 — ns M21 REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold 2 — ns REF_CLK (input) FEC_TX_EN M16 M17 M18 M19 M20 M21 FEC_RXD[1:0] FEC_TXD[1:0] (output) FEC_RX_ER CRS_DV (input) |
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