PCIMX258CJM4A datasheet(92/144 Pages) FREESCALE

92 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal

3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line

max_rise_time(ID No IC9) + data_setup_time(ID No IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus

specification) before the I2CLK line is released.

4 C

b = total capacitance of one bus line in pF.

Table 68. I2C Module Timing Parameters: 1.8 V +/– 0.10 V

Parameter

Standard Mode

Unit

Min.

Max.

IC1

I2CLK cycle time

μs

IC2

Hold time (repeated) START condition

4.0

μs

IC3

Set-up time for STOP condition

4.0

μs

IC4

Data hold time

1 A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the

falling edge of I2CLK.

3.452

2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal

μs

IC5

HIGH Period of I2CLK Clock

4.0

μs

IC6

LOW Period of the I2CLK Clock

4.7

μs

IC7

Set-up time for a repeated START condition

4.7

μs

IC8

Data set-up time

250

IC9

Bus free time between a STOP and START condition

4.7

μs

IC10

Rise time of both I2DAT and I2CLK signals

1000

IC11

Fall time of both I2DAT and I2CLK signals

300

IC12

Capacitive load for each bus line (Cb)-

400

PCIMX258CJM4A Datasheet(PDF) 92 Page - Freescale Semiconductor, Inc

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