PCIMX258CJM4A datasheet(83/144 Pages) FREESCALE

83 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

3.7.8

Enhanced Secured Digital Host Controller (eSDHCv2) Timing

Figure 54 shows eSDHCv2 timing, and Table 59 describes the timing parameters (SD1–SD8) used in the

figure. The following definitions apply to values and signals described in Table 59:

•

LS: low-speed mode. Low-speed card can tolerate clocks up to 400 kHz

•

FS: full-speed mode. Full-speed MMC card’s clock can reach 20 MHz; full speed SD/SDIO card

clock can reach 25 MHz

•

HS: high-speed mode. High-speed MMC card’s clock can reach 52 MHz; SD/SDIO card clock can

reach 50 MHz

SCKT rising edge to data out valid

—

18.0

13.0

x ck

i ck

SCKT rising edge to data out high

impedance6

——

—

21.0

16.0

x ck

i ck

SCKT rising edge to transmitter #0 drive

enable negation6

——

—

14.0

9.0

x ck

i ck

FST input (bl, wr) setup time before SCKT

falling edge5

——

2.0

18.0

—

x ck

i ck

FST input (wl) setup time before SCKT falling

edge

——

2.0

18.0

—

x ck

i ck

FST input hold time after SCKT falling edge

—

4.0

5.0

—

x ck

i ck

FST input (wl) to data out enable from high

impedance

—

21.0

—

FST input (wl) to transmitter #0 drive enable

assertion

—

14.0

—

Flag output valid after SCKT rising edge

—

14.0

9.0

x ck

i ck

HCKR/HCKT clock cycle

—

2 x TC

—

HCKT input rising edge to SCKT output

—

18.0

—

HCKR input rising edge to SCKR output

—

18.0

—

1 V

CORE_VDD = 1.00 ± 0.10 V; TJ = –40 °C to 125 °C, CL = 50 pF

2 In the “Characteristics” column, bl = bit length, wl = word length, wr = word length relative

3 In the “Expression” column, T

C = 7.5 ns.

4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

5 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but spreads starting from one serial clock before the first bit clock (same as the bit length frame sync signal),

until the second-to-last bit-clock of the first word in the frame.

6 Periodically sampled and not 100% tested.

Table 58. ESAI General Timing Requirements (continued)

No.

Characteristics1 2

Symbol

Expression3

Min.

Max.

Condition

Unit

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