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PCIMX258CJM4A Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 62 Page - Freescale Semiconductor, Inc |
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62 / 144 page ![]() i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 62 Freescale Semiconductor Figure 30. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram 3.7.6.1.3 DDR2 SDRAM–Specific Parameters The following diagrams and tables specify timing related to the SDRAMC module, which interfaces with DDR2 SDRAM. Table 47. Mobile DDR SDRAM Read Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD21 DQS – DQ Skew (defines the data valid window in read cycles related to DQS) tDQSQ — 0.85 ns SD22 DQS DQ HOLD time from DQS tQH 2.3 — ns SD23 DQS output access time from SDCLK posedge tDQSCK — 6.7 ns SDCLK SDCLK DQS (input) DQ (input) Data Data Data Data Data Data Data Data SD23 SD21 SD22 |
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