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PCIMX258CJM4A Datasheet(PDF) 84 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 84 Page - Freescale Semiconductor, Inc |
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84 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 84 Freescale Semiconductor Figure 54. eSDHCv2 Timing Table 59. eSDHCv2 Interface Timing Specification ID Parameter Symbols Min. Max. Unit Card Input Clock SD1 Clock frequency (low speed) fPP 1 1 In low-speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 0400 kHz Clock frequency (SD/SDIO full speed/high speed) fPP 2 2 In normal-speed mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. In high speed mode, clock frequency can be any value between 0 ~ 50 MHz. 0 25/50 MHz Clock frequency (MMC full speed/high speed) fPP 3 3 In normal-speed mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. In high speed mode, clock frequency can be any value between 0 ~ 52 MHz. 0 20/52 MHz Clock frequency (identification mode) fOD 100 400 kHz SD2 Clock low time tWL 6.5 — ns SD3 Clock high time tWH 6.5 — ns SD4 Clock rise time tTLH —3 ns SD5 Clock fall time tTHL —3 ns eSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 eSDHC output delay tOD –33ns eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD7 eSDHC input setup time tISU 2.5 — ns SD8 eSDHC input hold time tIH 4 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 2.5 — ns SD1 SD3 SD5 SD4 SD7 CMD output from eSDHCv2 to card DAT1 ...... DAT7 DAT0 CMD input from card to eSDHCv2 DAT1 ...... DAT3 DAT0 CLK SD2 SD8 SD6 |
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