PCIMX258CJM4A datasheet(42/144 Pages) FREESCALE

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

3.7

Module Timing and Electrical Parameters

This section contains the timing and electrical parameters for i.MX25 modules.

3.7.1

1-Wire Timing Parameters

Figure 7 shows the reset and presence pulses (RPP) timing for 1-Wire, and Table 30 lists the RPP timing

parameters.

Figure 7. 1-Wire RPP Timing Diagram

Figure 8 shows write 0 sequence timing, and Table 31 describes the timing parameters (OW5–OW6) that

are shown in the figure.

Figure 8. Write 0 Sequence Timing Diagram

2 Vid(ac) specifies the input differential voltage |Vtr–Vcp| required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The minimum value is equal to Vih(ac)–Vil(ac)

3 The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

4 The typical value of Vox(ac) is expected to be about 0.5 × OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)

indicates the voltage at which differential output signal must cross. Cload = 25 pF.

Table 30. RPP Sequence Delay Comparisons Timing Parameters

Parameters

Symbol

Min.

Typ.

Max.

Units

OW1

Reset Time Low

tRSTL

480

511

—

OW2

Presence Detect High

tPDH

—

OW3

Presence Detect Low

tPDL

—

240

OW4

Reset Time High

tRSTH

480

512

—

1-Wire bus

1-Wire Memory Device

“Presence Pulse”

(OWIRE_LINE)

1-Wire Tx

“Reset Pulse”

OW1

OW2

OW3

OW4

OW5

OW6

1-Wire bus

(OWIRE_LINE)

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