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PCIMX258CJM4A Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

Part # PCIMX258CJM4A
Description  i.MX25 Applications Processor for Consumer and Industrial Products
PDF  144 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PCIMX258CJM4A Datasheet(HTML) 91 Page - Freescale Semiconductor, Inc

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3
Freescale Semiconductor
91
3.7.11
Inter IC Communication (I2C) Timing
The I2C communication protocol consists of the following seven elements:
•Start
•
Data source/recipient
•
Data direction
•
Slave acknowledge
•Data
•
Data acknowledge
•
Stop
Figure 64 shows the timing of the I2C module. Table 67 and Table 68 describe the I2C module timing
parameters (IC1–IC6) shown in the figure.
Figure 64. I2C Module Timing Diagram
Table 67. I2C Module Timing Parameters: 3.0 V +/–0.30 V
ID
Parameter
Standard Mode
Fast Mode
Unit
Min.
Max.
Min.
Max.
IC1
I2CLK cycle time
10
-
2.5
μs
IC2
Hold time (repeated) START condition
4.0
-
0.6
-
μs
IC3
Set-up time for STOP condition
4.0
-
0.6
-
μs
IC4
Data hold time
01
1 A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
3.452
01
0.92
μs
IC5
HIGH Period of I2CLK Clock
4.0
-
0.6
-
μs
IC6
LOW Period of the I2CLK Clock
4.7
-
1.3
-
μs
IC7
Set-up time for a repeated START condition
4.7
-
0.6
-
μs
IC8
Data set-up time
250
-
1003
-ns
IC9
Bus free time between a STOP and START condition
4.7
-
1.3
-
μs
IC10
Rise time of both I2DAT and I2CLK signals
-
1000
20+0.1Cb
4
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
-
300
20+0.1Cb
4
300
ns
IC12
Capacitive load for each bus line (Cb)
-
400
-
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
START
I2DAT
I2CLK
IC1



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