PCIMX258CJM4A datasheet(52/144 Pages) FREESCALE

52 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

3.7.3

Digital Audio Mux (AUDMUX) Timing

The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between

internal serial interfaces (SSI and SAP) and external serial interfaces (audio and voice codecs). The AC

timing of AUDMUX external pins is governed by the SSI modules. For more information, see

Section 3.7.17, “Synchronous Serial Interface (SSI) Timing.”

3.7.4

CMOS Sensor Interface (CSI) Timing

The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as

dumb or smart as follows:

•

Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync

(HSYNC)) and output-only Bayer and statistics data.

•

Smart sensors support CCIR656 video decoder formats and perform additional processing of the

image (for example, image compression, image pre-filtering, and various data output formats).

The following subsections describe the CSI timing in gated and ungated clock modes.

3.7.4.1

Gated Clock Mode Timing

Figure 20 and Figure 21 shows the gated clock mode timings for CSI, and Table 39 describes the timing

parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on VSYNC, then

HSYNC is asserted and holds for the entire line. The pixel clock is valid as long as HSYNC is asserted.

Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge

PIXCLK

VSYNC

DATA[15:0]

HSYNC

PCIMX258CJM4A Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc