AFE5801 datasheet(35/46 Pages) TI

35 / 46 page

ReferenceClock

REF_IN

VCXO_INP

VCXO_INM

Y0B

VCXO

OUTP

OUTM

CTRL

CLKP

CLKM

AFE5801

CDCM7005

AFE5801

www.ti.com

SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

Figure 42. PECL Clock Drive Using CDCM7005

DIGITAL OUTPUTS

The conversion results from all eight ADCs are serialized and output using one LVDS data pair per ADC, at 12

times the device input clock rate. Besides that, two more LVDS pairs are used to facilitate the interface to the

circuit reading the ADC output. For one side, a reference frame LVDS signal running at the input clock rate

indicates the beginning and end of the sample word. On top of that, the device outputs a reference clock running

at 6 times the input clock rate, with rise and fall times aligned with the individual bits. See the Output Interface

Timing section for a description of the timing diagram as well as details on the timing margins.

Figure 43 represents the device LVDS output circuit. Observe that for an LVDS output high (OUTP = 1.375V,

OUTM = 1.025V) the high switches would be closed and the low switches would be open. For LVDS output low

(OUTP = 1.025V, OUTM = 1.375V) the low switches would be closed and the high left open. As the high and low

switches have a nominal RON of 50Ω ±10%, notice that the output impedance will be nominally 100Ω in any of

those two configurations (high or low switches closed).

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AFE5801 Datasheet(PDF) 35 Page - Texas Instruments