AFE5801 datasheet(33/46 Pages) TI

33 / 46 page

VCM

CLKP

CLKM

5 kW

VCM

AVDD18

AFE5801

www.ti.com

SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

ANTI-ALIAS FILTER (AAF)

The AFE5801 integrates a selectable third-order low-pass filter for each of the eight channels. The cutoff

frequency can be set for all the channels simultaneously through the serial interface (see FILTER_BW register, in

the General Purpose Register table) between 3 possible settings: 7.5, 10 and 14MHz. Figure 18 shows the

frequency response for each of these settings. The filter characteristics are set by passive components which are

subject to variations over process and temperature. A typical variation of ±5% on the frequency characteristics is

expected.

CLAMPING CIRCUIT AND OVERLOAD RECOVERY

The AFE5801 is designed in particular for ultrasound applications where the front-end device is required to

recover very quickly from an overload condition. Such overload can either be the result of a transmit pulse

feed-through or a strong echo, which can cause overload of the VGA and ADC.

Enabled by default, the AFE5801 includes a clamping circuit to further optimize the overload recovery behavior of

the complete channel (see Figure 34). The circuit can be disabled by writing a 1 in the bit 14 of the address 70

(decimal) of the General Purpose Register Map. The clamp is set to limit the signal at 3dB above the full scale of

the ADC (2Vpp).

CLOCK INPUTS

The eight channels on the device operate from a single clock input. To ensure that the aperture delay and jitter

are the same for all channels, the AFE5801 uses a clock tree network to generate individual sampling clocks to

each channel. The clock lines for all channels are matched from the source point to the sampling circuit of each

of the eight internal ADCs. The variation on this delay is described in the Aperture Delay parameter of the Output

Interface Timing. Its variation over time is described in the Aperture Jitter number of the same table.

The AFE5801 clock input can be driven differentially (sine wave, LVPECL or LVDS) or single-ended (LVCMOS).

The clock input of the device has an internal buffer/clock amplifier (see Figure 39) which is enabled or disabled

automatically depending on the type of clock provided (autodetect feature). When enabled, the device will

consume 6mW more power from the AVDD18 supply rail, but it will also accept differential or single ended inputs

of smaller swing.

Figure 39. Internal Clock Buffer for Differential Clock Mode

If the preferred clocking scheme for the device is single-ended, CLKINM pin should be connected to ground, i.e.,

shorted directly to AVSS (see Figure 41). In this case, the autodetect feature will shut down the internal clock

buffer and the device will go into single-ended clock input automatically. The user should connect the

single-ended clock source directly (no decoupling) to CLKINP pin, which would be the only device clock input. In

that case, it is recommended the use of low jitter square signals (LVCMOS levels, 1.8V amplitude) to drive the

ADC (see SLYT075 for further details on the theory).

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