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AFE5801 Datasheet(PDF) 25 Page - Texas Instruments |
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AFE5801 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 46 page  x x x x x x x x x x x x x x x x A7 A6 A5 A4 A3 A2 A1 A0 SEN SCLK SDATA SDOUT SDOUT tobeLatchedExternallyOntheRisingEdge StartSequence EndSequence t 7 t 6 t 2 t 4 t 1 t 5 t 3 T0385-01 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 AFE5801 www.ti.com SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010 OFFSET_CHi<9:2> = 0100 0000 means substract –128. For OFFSET_CHi<9:2> = 0111 1111 the effect is to substract 127. In effect, both addition and subtraction can be performed. Note that the the offset is applied before the digital gain (see DIGITAL_GAIN_ENABLE). The whole data path is 2s-complement throughout internally. Only when DFS = 1 (straight binary output format) is the 2s-complement word translated into offset binary at the end. REGISTER_READOUT_ENABLE Address: 0[1] The device includes an option where the contents of the internal registers can be read back. This may be useful as a diagnostic to verify the serial interface communication between the external controller and the AFE. First, the <REGISTER READOUT ENABLE> bit must be set to 1. Then user should initiate a serial interface cycle specifying the address of the register (A7–A0) whose content is to be read. The data bits are don't care. The device outputs the contents (D15–D0) of the selected register on the SDOUT pin. The external controller can latch the contents at the rising edge of SCLK. To enable serial register writes, set the <REGISTER READOUT ENABLE> bit back to 0. The following timing diagram shows this operation (the time specifications follow the same information provided on the table for a serial interface register write): Figure 37. Serial Interface Register Read Register readback is incorrect for address 0x97. See the INTERP_ENABLE section for details. SERIALIZED_DATA_RATE Address: 3[14:13] These two bits control the length of the data word, i.e., the number of DCLKs per FCLK period. It is possible, for instance, to output a 16bit data stream even with a 12bit ADC. In this case, the 4 LSBs are padded with 0s. The pass from higher resolution to lower serialization is not supported, however. I.e, it is not possible to select a 10bit stream with a 12bit ADC. TGC_REGISTER_WREN Address: 0[2] Set this bit to 1 to access the TGC table and 0 (default after reset) to access the general-purpose register table. The same address may point, this way, to one bank of registers (general purpose) or to the other (TGC control). Nevertheless, observe that register 0 of the general-purpose registers is always accessible, regardless of the value of TGC_REGISTER_WREN. The TGC table starts at address 1. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link(s): AFE5801 |
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