AFE5801 datasheet(17/46 Pages) TI

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AFE5801

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SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

APPLICATION INFORMATION

THEORY OF OPERATION

The AFE5801 is a very low-power CMOS monolithic analog front end which includes an eight-channel

variable-gain amplifier (VGA) followed by an eight-channel, 12bit, high-speed pipeline analog-to-digital convereter

(ADC) based on switched-capacitor architecture.

Each of the eight VGA differential inputs is buffered and accepts a maximum swing of 2Vpp centered at a dc

level (VCM) of about 1.6V.

Each VGA has a gain range from –5dB to 31dB, and the gain is digitally controlled, with a resolution of 0.125dB.

Using the serial interface, the gain curves (common to all VGAs) versus time can be stored in the memory

integrated within the device.

A hardware sync input pin is available (SYNC). When a pulse is applied to this pin, all the VGAs in the device

start stepping through the selected time-gain curve at the same clock cycle. This sync can also be initiated by

software using the serial interface.

A selectable anti-alias low-pass filter (AAF) with 3dB attenuation at 7.5MHz, 10MHz, or 14MHz is also integrated,

together with clamping (which can be disabled).

The VGA/AAF can output 2Vpp differential swing without degradation in the specified linearity and can drive an

onboard 12bit ADC. After the input signals are captured by the sample-and-hold circuit, at the rising edge of the

clock, the samples are sequentially converted by a series of low-resolution stages. The outputs of the stages are

combined in a digital correction logic block to form the final 12bit word with a latency of 11 clock cycles, without

taking into account the delays introduced by the optional digital signal-processing functions. These functions are,

in this order, offset correction, channel averaging, digital gain, and high-pass filtering (see General-Purpose

slower operation speeds, the AFE5801 offers the possibility of multiplexing up to two input channels into one

LVDS output stream, reducing even further the power consumption and routing area. In addition to the data

streams, a bit clock and frame clock are also output. The frame clock is aligned with the 12bit word boundary.

Notice that for the correct operation of the device (see the Serial Interface section), a positive pulse must be

applied to the RESET pin. This sets the internal control registers to zero. There is, nevertheless, no need for any

type of power-up sequencing.

INPUT CONFIGURATION

The analog input for the AFE5801, Figure 34, consists of a differential analog buffer which has inputs biased to

1.6V (usually refered as common-mode voltage, VCM). The biasing is done with two internal resistors of 5kΩ. For

proper operation, the input signal should be either ac-coupled or have a commn-mode value equal to VCM. In the

case of ac coupling, the external input capacitors form a high-pass filter with the internal bias resistors (5k

Ω), so,

the value of the capacitors should allow the lowest frequency of interest to pass with minimum attenuation. For

the typical frequencies used in ultrasound (>1MHz) a value of 10nF or bigger is recommended. If dc coupling is

preferred, the user can tap the VCM output pins to set the common-mode level of the input signal. The VCM output

should be connected to high-input-impedance circuits, as its driving capability is limited. Regardless of the

choosen input configuration, a capacitor of 100nF should be connected on each VCM input to AVSS.

For proper operation, the input signal should be in the recommended input range. The maximum input swing is

limited to 2Vpp before saturation/distortion fo the input stage occurs. As the input common mode (VCM) is about

1.6V, each input of the buffer should stay between 1.1V and 2.1V.

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