AFE5801 datasheet(19/46 Pages) TI

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T0108-04

PowerSupply

AVDD,LVDD

RESET

SEN

AFE5801

www.ti.com

SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

Reset Timing

Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,

AVDD3 = 3.3V, AVDD18 = DVDD18 = 1.8V, unless otherwise noted.

PARAMATER

CONDITIONS

MIN

TYP

MAX

UNIT

Delay from power-up of AVDD and LVDD to RESET pulse

Power-on delay time

active

Reset pulse width

Pulse width of active RESET signal

tPO

Power-up delay time

Delay from power-up of AVDD and LVDD to output stable

6.5

Figure 35. Reset Timing

Programming of different modes can be done through the serial interface formed by pins SEN (serial interface

enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. SCLK and SDATA have a

100k

Ω pulldown resistor to ground, and SEN has a 100kΩ pullup resistor to DVDD18. Serial shift of bits into the

device is enabled when SEN is low. Serial data SDATA is latched at every rising edge of SCLK when SEN is

active (low). The serial data is loaded into the register at every 24th SCLK rising edge when SEN is low. In case

the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24bit words within a single active SEN pulse (there is an internal counter that counts groups of 24 clocks after

the falling edge of SEN). The interface can work with SCLK frequency from 20MHz down to very low speeds (a

few Hertz) and even with a non-50% duty-cycle SCLK.

The data is divided in two main portions: a register address (8 bits) and the data itself, to load on the addressed

SDOUT signal outputs zeros. The following timing diagram illustrates this process.

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