AFE5801 datasheet(18/46 Pages) TI

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INP

Vcm

Clamp

Coupling

Internal

Voltage

Reference

CMBuffer

5kW

INM

Channel

Input

AFE5801

SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

www.ti.com

NOTE: Dashed area denotes one of eight channels.

Figure 34. Common-Mode Biasing of Input Pins

The maximum input swing is limited to 2Vpp before distortion/saturation of the input stage occurs. As the input dc

level (VCM) is about 1.6V, this means that each input of the VGA typically stays between 1.1V and 2.1V.

To drive the AFE5801 with a single-ended signal, the signal should be connected to one of the inputs (INiP, in

principle, to keep the polarity) and the other connected to AVSS through a 100nF capacitor. In fact, all the

AFE5801 inputs that must be connected to ground can be shorted together and connected to ground through a

single 100nF capacitor. The input is limited to 1Vpp (from 1.1V to 2.1V) and the performance is similar to that of

the AFE5851. Every channel on the AFE5851 is similar to a channel on the AFE5801 where the other input has

been shorted internally to VCM. See the AFE5851 16 Channel Variable Gain Amplifier (VGA) With Octal High

Speed ADC data sheet (SLOS574) for more information.

SERIAL INTERFACE

After power up, the internal registers must be initialized to the default value (zero). Initialization can be done in

one of two ways:

•

Through a hardware reset, by applying a positive pulse in the RESET pin

•

Through a software reset, using the serial interface, by setting the SOFTWARE RESET bit to high. Setting

this bit initializes the internal registers to the respective default values (all zeros) and then self-resets the

SOFTWARE RESET bit to low. In this case, the RESET pin can stay low (inactive).

It is important to notice that after power up and before the device is reset to its default state, the power

consumption could be up to 2× the specified maximum, due to the unknown setting of the internal registers. In

order to prevent the initial increased power consumption, a potential solution is to connect the RESET pin to

either 1.8V or 3.3V supply with a 10k

Ω resistor, so that the device is reset while powering up. For the reset to

take effect, the power must be up on DVDD18. Notice that there is no damage to the part by applying voltage

to the RESET pin while the device power is off.

Notice also that the reset only affects the digital registers, putting the part in its default state. It does not act

as a power down and as such, everything internal just keeps running. As the internal registers change their

values, the effects on the data propagate through the pipe. At the same time, there may be some glitches on

the output due to the transition of the registers values if any of the output controlling modes, for instance,

change. As the reset is level-sensitive and asynchronous with the input clock, it should be inactive in order to

write into the internal registers. Although it takes only 10ns after the reset rising edge to change the registers,

the output data may take, in the worst case, up to 20 clock cycles to be considered stable. Notice that the

output clocks (data and frame) are independent of the RESET and tight to the input clock, avoiding any loss

of synchronization.

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