AFE5801 datasheet(22/46 Pages) TI

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AFE5801

SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

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GENERAL-PURPOSE REGISTER DESCRIPTION

AVERAGING_ENABLE

Address: 2[11]

When set to 1, two samples, corresponding to two consecutive channels, are averaged (channel 1 with 2, 3

with 4, 5 with 6, and 7 with 8). If both channels receive the same input, the net effect is an improvement in

SNR. The averaging is performed as:

•

Channel 1 + channel 2 comes out on channel 3.

•

Channel 3 + channel 4 comes out on channel 4.

•

Channel 5 + channel 6 comes out on channel 5.

•

Channel 7 + channel 8 comes out on channel 6.

DFS

Address: 4[3]

DFS stands for data format select. The ADC output, by default, is in 2s-complement mode. Programming the

DFS bit to 1 inverts the MSB, and the output becomes straight-offset binary mode.

DIGITAL_GAIN_ENABLE

Address: 3[12]

Setting this bit to 1 applies to each channel i the corresponding gain given by DIG_GAINi<15:11>. The gain

is given as 0dB + 0.2dB × DIG_GAINi<15:11>. For instance, if DIG_GAIN5<15:11> = 3, channel 5 is

increased by 0.6dB gain. DIG_GAINi<15:11> = 31 produces the same effect as DIG_GAINi<15:11> = 30,

setting the gain of channel i to 6dB.

DIGITAL_HIGH_PASS_FILTER_ENABLE and DIGITAL_HIGH_PASS_FILTER_CORNER_FREQ

DIGITAL_HIGH_PASS_FILTER_ENABLE (channels 1–4): Address: 21[0]

DIGITAL_HIGH_PASS_FILTER_ENABLE (channels 5–8): Address: 33[0]

DIGITAL_HIGH_PASS_FILTER_CORNER_FREQ (channels 1–4): Address: 21[4:1]

DIGITAL_HIGH_PASS_FILTER_CORNER_FREQ (channels 5–8): Address: 33[4:1]

This group of four registers controls the characteristics of a digital high-pass transfer function applied to the

output data, following the formula: y(n) = 2k/(2k + 1) [x(n) – x(n – 1) + y(n – 1)]. The

DIGITAL_HIGH_PASS_FILTER_CORNER_FREQ registers (one for the first four channels and one for the

second group of four channels) describe the setting of k.

EXTERNAL_REFERENCE

Address: 1[13]

The internal reference mode (default) uses approximately 3mW more power on AVDD (which is already

included in all the specification tables). The AFE5801 can operate in external reference mode by

programming EXTERNAL_REFERENCE to 1. In this mode, the VREF_IN pin should be driven with 1.4V.

Due to the high input impedace of this pin, no special drive capabilities are required. For the same reason,

no decoupling on VREF_IN is needed, although depending on the noise on the 1.4V signal, some filtering

may be required. Nevertheless, when using the internal reference, there is no need to decouple VREF_IN.

The advantage of using the external reference mode is that multiple AFE5801 units can be made to operate

with the same external reference, thereby improving parameters such as gain matching across devices.

FILTER_BW

Address: 7[3:2]

This bit sets the 3dB attenuation frequency for the antialiasing filter (AAF).

GLOBAL_PDN

Address: 1[0]

The global PDN bit is ORed with the signal in the external PDN pin (59). Therefore, a 1 on this bit shuts the

device down completely.

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