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AFE5801 Datasheet(PDF) 32 Page - Texas Instruments

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Part # AFE5801
Description  8-Channel Variable-Gain Amplifier (VGA) With Octal High-Speed ADC
PDF  46 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AFE5801 Datasheet(HTML) 32 Page - Texas Instruments

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AFE5801
SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010
www.ti.com
NAME
VALUE
START_INDEX
0x02
STOP_INDEX
0x07
START_GAIN
0x06
HOLD_GAIN_TIME
0x04
INTERP_ENABLE
1
UNIFORM_GAIN_MODE
0
Uniform Gain Increment Mode
By setting UNIFORM_GAIN_MODE to 1, the TGC engine can also be configured for a uniform increment gain
ramp mode where the gain is ramped up from the START_GAIN value to the STOP_GAIN with a slope set by
the UNIFORM_GAIN_SLOPE register. Note: STOP_GAIN is not a programmable register, but just an internally
computed value from START_GAIN, UNIFORM_GAIN_SLOPE, START_INDEX and STOP_INDEX.
If INTERP_ENABLE = 1, UNIFORM_GAIN_SLOPE sets the number of Tclk (channel sampling clock) at a given
gain before incrementing or decrementing 0.125dB. If INTERP_ENABLE = 0, this register sets the number of 8 ×
Tclk (eight sampling periods) at a given gain before incrementing or decrementing 1dB. Observe that in both
cases the time it takes to step by 1dB is the same. In INTERP_ENABLE = 0 the gain is stationary at the same
setting for the given time, whereas in the other case the gain increments in fine gain steps of 0.125dB to cover
that 1dB step
When
INTERP_ENABLE
is
zero,
the
STOP_GAIN
is
computed
as
START_GAIN
+
(STOP_INDEX-START_INDEX). Nevertheless, when INTERP_ENABLE = 1, the STOP_GAIN is equal to
START_GAIN + (STOP_INDEX - START_INDEX) + 0.875dB. This is basically due to the fact that the
interpolation engine keeps the gain increasing on the second case, while, as explained above, is frozen on the
first case. Observe that START_INDEX and STOP_INDEX are not used in this case as pointers to the
REG_VALUEs table. Instead, only the difference between the two is important to compute STOP_GAIN. As
such, START_INDEX can be set to zero and STOP_INDEX will store STOP_GAIN – START_GAIN. Observe
that only positive slope ramps are possible.
Example
1:
setting
START_GAIN
=
0x2
(–3dB),
START_INDEX
=
0x00,
STOP_INDEX
=
0x06,
INTERP_ENABLE = 0 and UNIFORM_GAIN_SLOPE = 0x8, will set the gain at –3dB for 8 × 8 × Tclk, then to
–2dB for another 64 Tclk, and so on, through –1, 0, 1, 2 and 3. After spending 64 × Tclk in 3dB, the gain will stay
at that gain setting for HOLD_GAIN_TIME and start stepping down back to START_GAIN, with 1dB per Tclk.
Example 2: for the same settings, START_GAIN = 0x2 (–3dB), START_INDEX = 0x00, STOP_INDEX = 0x06,
and UNIFORM_GAIN_SLOPE = 0x8, if we set INTERP_ENABLE = 1, the gain will start at –3dB for 8Tclk, then
–2.875dB for another 8Tclk, then –2.750dB and so on, till 3dB. At this point, while in example 1, with
INTERP_ENABLE = 0 the gain would be frozen for another 64 Tclk, in this example, the gain will continue to
increase with 0.125dB steps every 8Tclk till 3.875dB is reached. There will stay for another 8Tclk before starting
to wait for HOLD_GAIN_TIME and start stepping down.
Example 3: for START_GAIN = 0x2 (–3dB) , START_INDEX = 0x00, STOP_INDEX = 0x00, INTERP_ENABLE =
1 and UNIFORM_GAIN_SLOPE = 0x1, the gain will step through –3dB, –2.875, –2.75, –2.625, –2.5, –2.375,
–2.25 and –2.125, staying at each of these 8 values 1 clock cycle (8 total). Then it will wait for
HOLD_GAIN_TIME in –2.125dB and then it will start stepping down back to –3dB.
Example 4: same settings as example 3, but with INTERP_ENABLE = 0, would simply set the VGA gain to –3dB
for 8 clock cycles and then the logic would wait for HOLD_GAIN_TIME.
Static PGA Mode
The 3rd mode of operation is actually a mode where the TGC engine is disabled by writing 1 into the
STATIC_PGA bit. This enables the use of a fixed gain mode where the gain is obtained by the sum of a coarse
and a fine gain. Coarse gain can be set from –5 to 31dB, in 1dB steps, by the register COARSE_GAIN (6 bit
word from 0x00 to 0x24). Setting a value bigger than 0x24 on the COARSE_GAIN register is the same as setting
0x24. The fine gain can be set in steps of 0.125dB resolution, from 0dB to 0.875dB by the FINE_GAIN register (3
bit word with range from 0x00 to 0x07). Observe that the maximum gain, when both registers are set to their
maximum gains, is actually 31.875dB.
32
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