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AFE5801 Datasheet(PDF) 39 Page - Texas Instruments

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Part # AFE5801
Description  8-Channel Variable-Gain Amplifier (VGA) With Octal High-Speed ADC
PDF  46 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AFE5801 Datasheet(HTML) 39 Page - Texas Instruments

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AFE5801
www.ti.com
SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010
REVISION HISTORY
Changes from Revision C (January 2010) to Revision D
Page
•
Deleted INVERT_CHANNEL and MSB_FIRST rows from register map table ................................................................... 21
•
Deleted INVERT_CHANNEL register description ............................................................................................................... 23
•
Deleted MSB_FIRSTL register description ......................................................................................................................... 23
Changes from Revision B (April 2009) to Revision C
Page
•
Added pullup/pulldown resistors to descriptions of PDN, RESET, SCLK, SDATA, SEN, and SYNC terminals .................. 3
•
Added a note to the TERMINAL FUNCTIONS table, referenced from pin 28 within the table ............................................ 3
•
Listed names of digital control pins and changed maximum voltage rating for them ........................................................... 4
•
Added a minimum value for LVDS ac-coupled clock input in RECOMMENDED OPERATING CONDITIONS ................... 5
•
Added rows for VIH and VIL to CLOCK INPUT section of RECOMMENDED OPERATING CONDITIONS table ................ 5
•
Added note to ELECTRICAL CHARACTERISTICS table regarding the effects of enabling clamping ................................ 5
•
Added note to ELECTRICAL CHARACTERISTICS table regarding the effects of enabling clamping ................................ 6
•
Added note to ELECTRICAL CHARACTERISTICS table for IDVDD18 row in POWER section .............................................. 6
•
Listed names of digital-input and digital-output pins in Digital Characteristics table ............................................................ 7
•
Added section for SDOUT to Digital Characteristics table ................................................................................................... 7
•
Added a reference to Recommended Operating Conditions table to the note following the Digital Characteristics
table ...................................................................................................................................................................................... 7
•
Added note for FCLK timing to Output Interface Timing table .............................................................................................. 8
•
Modified next-to-last paragraph in Theory of Operation section ......................................................................................... 17
•
Added a new paragraph to the end of the Input Configuration section .............................................................................. 18
•
Added two new paragraphs to the end of the Register Initialization section ...................................................................... 18
•
Added a sentence to the last paragraph of the Reset Timing section ................................................................................ 19
•
Changed "Serial Interface Register Write" from a section heading to a figure caption ...................................................... 20
•
Added a parenthetical expression to a sentence in the General-Purpose Register Map section ...................................... 20
•
Deleted text from ADDRESS 3[8] DESCRIPTION ............................................................................................................. 21
•
Changed DESCRIPTION for ADDRESS 7[8:7] in register map. ........................................................................................ 21
•
Added two sentences to EXTERNAL_REFERENCE register description .......................................................................... 22
•
Changed address of LOW_FREQUENCY_NOISE_SUPPRESSION to 1[11] ................................................................... 23
•
Added reference to INTERP_ENABLE section .................................................................................................................. 25
•
Added a NOTE explaining readback from address 0x97 ................................................................................................... 28
•
Arranged TGC control register-description sections in alphabetical order by register name ............................................. 29
•
Changed "16 channels" to "eight channels" in the ANTI-ALIAS FILTER (AAF) section .................................................... 33
•
Changed "16 channels" to "eight channels" in the CLOCK INPUTS section ..................................................................... 33
•
Changed "clock channels" to "clock lines" in the Clock Inputs section .............................................................................. 33
•
Deleted two sentences from first paragraph of CLOCK INPUTS section ........................................................................... 33
Copyright © 2008–2010, Texas Instruments Incorporated
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