AFE5801 datasheet(23/46 Pages) TI

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AFE5801

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SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

INTERNAL_AC_COUPLING

Address: 7[1]

This bit controls an internal high-pass filter (Figure 34), set between the input buffer and the VCA. This filter

removes the input offset to avoid its amplification by the TGC. An alternative method is to remove the offset

effect on the digital domain, either on the device following the ADC or at the ADC output, by using the

DIGITAL HIGH PASS FILTER registers described previously.

LOW_FREQUENCY_NOISE_SUPPRESSION

Address: 1[11]

The low-frequency noise-suppression mode is specifically useful in applications where good noise

performance is desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the

low-frequency noise of the ADC in the AFE5801 to approximately fS/2, thereby reducing the noise floor

around dc to a much lower value.

OUTPUT_DISABLE

Address: 1[1]

A 1 on this bit sets all the LVDS outputs into the high-impedance state.

OUTPUT_RATE_2X

Address: 1[14]

The output data always uses a DDR format, with valid/different bits on the positive as well as the negative

edges of the LVDS bit clock, DCLK. The output rate is set by default to 1× (OUTPUT_RATE_2X = 0), where

each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share

one LVDS stream, in this way lowering the power consumption devoted to the interface. The unused outputs

will output zero. To avoid consumption from those outputs, no termination should be connected to them. The

distribution on the used output pairs is done in the following way:

•

Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first.

•

Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first.

•

Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first.

•

Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first.

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