AFE5801 datasheet(21/46 Pages) TI

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AFE5801

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SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

ADDRESS

FUNCTION

DESCRIPTION

1[10]

STDBY

0: Power up. 1: Standby (fast power-up mode)

1[9:2]

PDN CHANNEL<7:0>

PDN for each individual channel (VCA+ADC). LVDS outputs logic 0.

1[1]

OUTPUT_DISABLE

0: Ouptut enabled. 1: Output disabled

1[0]

GLOBAL_PDN

0: Power up. 1: Global power down (slow power-up mode)

2[15:13]

PATTERN_MODES

Pattern modes for serial LVDS. 000: No pattern. 001: Sync. 010: Deskew.

011: Custom reg. 100: All 1s. 101: toggle. 110: All 0s. 111: Ramp

2[11]

AVERAGING_ENABLE

0: Default (no averaging). 1: Average two channels to increase SNR.

2[10:3]

PDN_LVDS

Power down the eight data-output LVDS pairs.

3[14:13]

SERIALIZED_DATA_RATE

Serialization factor. 00: 12×. 01: 10×. 10: 16×. 11: 14×

3[12]

DIGITAL_GAIN_ENABLE

0: Default (no gain). 1: Apply digital gain set by the following registers.

3[8]

REGISTER_OFFSET_SUBTRACTION_

0: Default (no subtraction). 1: Subtract offset value set in the corresponding

ENABLE

registers.

4[3]

DFS

Data format select. 0: 2s complement. 1: Offset binary

5[13:0]

CUSTOM_PATTERN

Custom pattern data for LVDS (PATTERN_MODES = 011)

7[10]

VCA_LOW_NOISE_MODE_(INCREASE_

0: Low power. 1: Low noise, at the expense of increased power (5mW/channel)

POWER)

7[8:7]

SELF_TEST

00 or 10: No self-test. 01: Self-test enabled. 100 mV dc applied to the input of

the channels. 11: Self-test enabled. 150 mV dc applied to the input of the

channels. NOTE: DC applied before the input buffer. Test does not work if input

is dc-shorted to a different potential. Also notice that the

INTERNAL_AC_COUPLING bit is automatically set to 1 when entering this

mode, and reset back to whatever value it had before, when leaving this mode.

7[3:2]

FILTER_BW

00: 14MHz. 01: 10MHz. 10: 7.5MHz. 11: Not used.

7[1]

INTERNAL_AC_COUPLING

VGA coupling. 0: AC-coupled. 1: DC-coupled

13[15:11]

DIG_GAIN1

0dB to 6dB in steps of 0.2dB

13[9:2]

OFFSET_CH1

Value to be subtracted from channel 1

15[15:11]

DIG_GAIN2

0dB to 6dB in steps of 0.2dB

15[9:2]

OFFSET_CH2

Value to be subtracted from channel 2

17[15:11]

DIG_GAIN3

0dB to 6dB in steps of 0.2dB

17[9:2]

OFFSET_CH3

Value to be subtracted from channel 3

19[15:11]

DIG GAIN4

0dB to 6dB in steps of 0.2dB

19[9:2]

OFFSET_CH4

Value to be subtracted from channel 4

21[4:1]

DIGITAL_HIGH_PASS_FILTER_CORNER_

Sets k for the high-pass filter as desribed in General-Purpose Register

FREQ_FOR_CHANNELS-1–4

Description (k from 2 to 10).

21[0]

DIGITAL_HIGH_PASS_FILTER_ENABLE_

0: No high-pass filter. 1: High-pass filter enabled

FOR_CHANNELS_1–4

25[15:11]

DIG_GAIN8

0dB to 6dB in steps of 0.2dB

25[9:2]

OFFSET_CH8

Value to be subtracted from channel 5

27[15:11]

DIG_GAIN7

0dB to 6dB in steps of 0.2dB

27[9:2]

OFFSET_CH7

Value to be subtracted from channel 6

29[15:11]

DIG_GAIN6

0dB to 6dB in steps of 0.2dB

29[9:2]

OFFSET_CH6

Value to be subtracted from channel 7

31[15:11]

DIG_GAIN5

0dB to 6dB in steps of 0.2dB

31[9:2]

OFFSET_CH5

Value to be subtracted from channel 8

33[4:1]

DIGITAL_HIGH_PASS_FILTER_CORNER_

Sets k for the high-pass filter as desribed in General-Purpose Register

FREQ_FOR_CHANNELS_5–8

Description (k from 2 to 10).

33[0]

DIGITAL_HIGH_PASS_FILTER_ENABLE_

0: No high-pass filter. 1: High-pass filter enabled

FOR_CHANNELS_5–8

70[14]

CLAMP_DISABLE

0: Enabled. 1: Disabled

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