AFE5801 datasheet(28/46 Pages) TI

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AFE5801

SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

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INTERP_ENABLE

Address: 0x97[7]

This 8 bit register sets the ramp rate. When INTERP_ENABLE = 1, the ramp rate is 0.125dB for every

number of clocks stored in REG_VALUE:

REG_VALUE

SLOPE

0x0

0.125dB per Tclk

0x1

0.125dB per Tclk

0x2

0.125dB per 2 × Tclk

0xFF

0.125dB per 255 × Tclk

When INTERP_ENABLE = 0 the ramp rate is 1dB for every 8 times the number of clocks stored in REG_VALUE:

REG_VALUE

SLOPE

0x0

1dB per 8 × Tclk

0x1

1dB per 8 × Tclk

0x2

1dB per 16 × Tclk

0xFF

1dB per 255× 8 × Tclk

NOTE

Reading back the address 0x97 (INTERP_ENABLE) to verify its value shows the opposite

value of what it actually is. For instance, after setting INTERP_ENABLE to 1 in addres

0x97 to enable interpolation, the bit shows as 0 when reading it back from the same

address (0x97). After setting INTERP_ENABLE to 0 in addres 0x97 to disable

interpolation, the bit shows as 1 when reading it back.

SOFT_SYNC

Address 0x99[5]

Setting SOFT_SYNC bit to 1 enables the TGC engine to run periodically following a given TGC curve,

without the need for a high pulse signal in the SYNC pin (see more details in the Soft Synchronization

section).

UNIFORM_GAIN_MODE

Address 0x99[4]

Setting this bit to 0 (default) directs the TGC engine to follow an arbitrary gain-versus-time curve. If this bit is

set to 1, the gain is ramped up with a slope set by the UNIFORM_GAIN_SLOPE register. (See more details

in the Uniform Gain Increment Mode section.)

UNIFORM_GAIN_SLOPE

Address 0x9B[7:0]

See the Uniform Gain Increment Mode section.

STATIC_PGA

Address 0x99[3]

Setting this bit to 1 disables the TGC engine. COARSE_GAIN and FINE_GAIN control the gain value, which

is independent of time.

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