AFE5801 datasheet(24/46 Pages) TI

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AFE5801

SLOS591D – SEPTEMBER 2008 – REVISED MAY 2010

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PATTERN_MODES and CUSTOM_PATTERN

PATTERN_MODES: Address: 2[15:13]

CUSTOM_PATTERN: Address: 5[13:0]

The AFE5801 can output a variety of test patterns on the LVDS outputs. These test patterns replace the

normal ADC data output and help on debugging and synchronization, with the device reading the output of

the ADC.

•

PATTERN_MODE equal to 000 is the default and disables this test mode, i.e., the output data is the

same as the ADC data.

•

PATTERN_MODE equal to 001 (SYNC mode) replaces the normal ADC word by a fixed 1111 1100 0000

word.

•

PATTERN_MODE equal to 010 sets the DESKEW mode, where the 12-bit ADC output D<11:0> is

replaced with the 0101 0101 0101 word, which creates a continuous stream of 1s and 0s in the data line.

•

PATTERN_MODE equal to 011 outputs a constant code set by the bits in CUSTOM_PATTERN<13:0>.

Depending on the value of SERIALIZED_DATA_RATE (see following) the output bits conform to the

following rules:

–

In the default case, where SERIALIZED_DATA_RATE is 00, for 12-bit ADC data at the output, the

CUSTOM_PATTERN<13:2> bits are used, replacing the sampled data. These bits are still controlled

by the LSB-first and MSB-first modes in the same way as normal ADC data are.

–

For

SERIALIZED_DATA_RATE

01,

10-bit

output

mode

selected,

and

the

CUSTOM_PATTERN<13:4> bits are used.

–

For

SERIALIZED_DATA_RATE

10,

16-bit

output

mode

selected.

this

case,

the

CUSTOM_PATTERN<13:0> bits are used for the first 14 most-significant bits, and two 0s take the

place of the LSBs.

–

For SERIALIZED_DATA_RATE = 11, 14-bit mode is selected, and the CUSTOM_PATTERN<13:0>

bits take the place of the output word.

•

PATTERN_MODE equal to 100 makes the output always 1, whereas setting it to 110 makes the output

always 0.

•

PATTERN_MODE equal to 101 makes the output of the device toggle between two consecutive codes.

On the nth sample clock, the data is 0000 0000 0000, and on the following one (nth + 1), it is

1111 1111 1111.

•

PATTERN_MODE equal to 111 causes all the channels to output a repeating full-scale ramp pattern. The

ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the

full-scale code, it returns back to the zero code and ramps again.

PDN_CHANNEL<7:0>

Address: 1[9:2]

Each bit controls the power down of a channel (buffer, VCA, and ADC). For example, PDN_CHANNEL<0>

powers down channel 1 and the corresponding LVDS pair becomes high-impedance. DCLK and FCLK are

not powered down. They become active if terminated with 100

Ω.

PDN_LVDS

Address: 2[10:3]

PDN_LVDS<7:0> selects which LVDS pairs become inactive (zero output current, i.e., high-impedance

state). The frame and clock LVDS streams are powered down only when OUTPUT_DISABLE and/or

GLOBAL_PDN is set.

REGISTER_OFFSET_SUBTRACTION_ENABLE

Address: 3[8]

Setting this bit to 1 enables the substraction of the value on the corresponding OFFSET_CHi<9:2> (offset for

channel i) from the ADC output. The number is specified in 2s-complement format. For example,

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