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MAC7200 Datasheet(PDF) 486 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 486 Page - Freescale Semiconductor, Inc |
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486 / 976 page ![]() External Signal Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 408 Freescale Semiconductor 22.2.2 Detailed Signal Descriptions Check device level specification for connectivity of the signals. 22.2.2.1 VDDR - Regulator Power Input Signal VDDR is the power input of VREG_HIP7A. All currents sourced into the regulator loads flow through this pin. A chip external decoupling capacitor (100nF...220nF, X7R ceramic) between VDDR and VSS can smooth ripple on VDDR. For entering Shutdown Mode pin VDDR should also be tied to ground on devices without VREGEN pin. 22.2.2.2 VDDA, VSSA - Regulator Reference Supply Signals VDDA/VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100nF...220nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply. 22.2.2.3 VDD15, VSS15 - Regulator Output1 (Core Logic) Signals VDD15/VSS15 are the primary outputs of VREG_HIP7A that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100nF...220nF, X7R ceramic). In Shutdown Mode an external supply driving VDD15/VSS15 can replace the voltage regulator. Table 22-1. VREG_HIP7A - Signal Properties Name Function Reset State Pull up VDDR VREG_HIP7A power input (positive supply) — — VDDA VREG_HIP7A quiet input (positive supply) — — VSSA VREG_HIP7A quiet input (ground) — — VDD15 VREG_HIP7A primary 1.5V output (positive supply) — — VSS15 VREG_HIP7A primary 1.5V output (ground) — — VDD33 VREG_HIP7A primary 3.3V output (positive supply) — — VSS33 VREG_HIP7A primary 3.3V output (ground) — — VDDPLL VREG_HIP7A secondary 3.3V output (positive supply) — — VSSPLL VREG_HIP7A secondary 3.3V output (ground) — — VREGEN (optional) VREG_HIP7A (Optional) Regulator Enable — — |
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