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MAC7200 Datasheet(PDF) 518 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 518 Page - Freescale Semiconductor, Inc

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CRG Bus Aborts
MAC7200 Microcontroller Family Reference Manual, Rev. 2
440
Freescale Semiconductor
23.4.6.2
PLL Lock Interrupt
The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from
a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by clearing the
LOCKIE bit to zero. The PLL Lock interrupt flag (LOCKIF) is set to 1 when the LOCK condition has
changed and is cleared to 0 by writing a 1 to the LOCKIF bit.
23.4.6.3
Self Clock Mode Interrupt
The CRG generates a Self Clock Mode interrupt when the SCM condition of the system has changed;
either entered or exited Self Clock Mode. SCM conditions can only change if the Clock Monitor Reset
Disable (CMRD) bit is set to 1. SCM conditions are caused by a failing clock quality check after power
on reset (POR) or low voltage reset (LVR) or Clock Monitor failure. For details on the clock quality check,
refer to Section 23.4.2.4, “Clock Quality Checker.” If the clock monitor is enabled (CME=1) a loss of
external clock will also cause a SCM condition (CMRD=1).
SCM interrupts are disabled locally by setting the SCMIE bit to zero. The SCM interrupt flag (SCMIF) is
set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
23.5
CRG Bus Aborts
The CRG module supports Peripheral Bus bus aborts, and enforces the following memory map:
Supervisor Access: Unused.
23.6
CRG Differences from MAC71xx
•
Fixed MUCts01648: Write on bus abort still writes the register
•
Added single register with all possible reset sources
— Added the ILR, JTR, SFR, CMR, EXR and WDR bits to the CTFLG register
•
Removed Pseudo-STOP/STOP modes (DOZE still implemented)
— Removed the STPEF bit from the CRGFLG register
— Removed the PSTP bit from the CLKSEL register
Table 23-15. CRG Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
LOCK interrupt
I bit
CRGINT (LOCKIE)
SCM interrupt
I bit
CRGINT (SCMIE)
Table 23-16. CRG Bus Aborts
Abort
Allowed
$0000-$000b
$000c-$3fff



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