MAC7200 datasheet(514/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

436

Freescale Semiconductor

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Power on is detected

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Low voltage is detected

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SWT watchdog times out

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Clock monitor failure is detected and Self-Clock Mode was disabled (CMRD=0)

Upon detection of any reset event, an internal circuit drives the RESET pin low for 256 SYSCLK cycles

(see Figure ). Since entry into reset is asynchronous, it does not require a running SYSCLK. However, the

internal reset circuit of the CRG cannot sequence out of the current reset condition without a running

SYSCLK. The number of 256 SYSCLK cycles might be increased by n=3 to 6 additional SYSCLK cycles

depending on the internal synchronization latency. After 256+n SYSCLK cycles the RESET pin is

released. The reset generator of the CRG waits for an additional 64 SYSCLK cycles and then samples the

RESET pin to determine the originating source. Figure 23-14 shows which vector will be fetched.

NOTE

External circuitry connected to the RESET pin should not include a large

capacitance that would interfere with the ability of this signal to rise to a

valid logic one within 64 SYSCLK cycles after the low drive is released.

The internal reset of the MCU remains asserted while the reset generator completes the 320 SYSCLK long

reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted

synchronously after completion of the 320 SYSCLK cycles. When the RESET pin is externally driven low

for more than these 320 SYSCLK cycles (External Reset), the internal reset also remains asserted.

Table 23-14. Reset Vector Selection

sampled RESET pin

(64 cycles after

release)

Clock Monitor

Reset pending

SWT Reset

pending

Vector fetch

POR / LVR / External Reset

Clock Monitor Reset

SWT Reset

POR / LVR / External Reset

with rise of RESET pin

MAC7200 Datasheet(PDF) 514 Page - Freescale Semiconductor, Inc