MAC7200 datasheet(512/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

434

Freescale Semiconductor

Clock failure

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Scenario 1: OSCCLK recovers prior to exiting Doze Mode

– MCU remains in Doze Mode

– VREG enabled

– PLL enabled

– SCM activated

– Start Clock Quality Check

– Set SCMIF interrupt flag

Some time later OSCCLK recovers

– CM no longer indicates a failure

– 4096 OSCCLK cycles later Clock Quality Check indicates clock ok

– SCM deactivated

– PLL disabled depending on PLLDOZE

– VREG remains enabled (never gets disabled in Doze Mode)

– MCU remains in Doze Mode

Some time later either a wakeup interrupt occurs (no SCM interrupt)

– Exit Doze Mode using OSCCLK as system clock (SYSCLK)

– Continue normal operation

or an External Reset is applied

– Exit Doze Mode using OSCCLK as system clock

– Start reset sequence

Scenario 2: OSCCLK does not recover prior to exiting Doze Mode

– MCU remains in Doze Mode

– VREG enabled

– PLL enabled

– SCM activated

– Start Clock Quality Check

– Set SCMIF interrupt flag

– Keep performing Clock Quality Checks (could continue infinitely) while in Doze Mode

Some time later either a wakeup interrupt occurs (no SCM interrupt)

– Exit Doze Mode in SCM using PLL clock (fSCM) as system clock

– Continue to perform additional Clock Quality Checks until OSCCLK is ok again

or an External RESET is applied

– Exit Doze Mode in SCM using PLL clock (fSCM) as system clock

– Start reset sequence

– Continue to perform additional Clock Quality Checks until OSCCLK is ok again

Table 23-11. Outcome of Clock Loss in Doze Mode (Continued)

CME

CMRD

SCMIE

CRG Actions

MAC7200 Datasheet(PDF) 512 Page - Freescale Semiconductor, Inc

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