MAC7200 datasheet(509/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

431

If the CME bit is disabled and the MCU is configured to run on the PLL

clock (PLLCLK), a loss of external clock (OSCCLK) will not be detected

and will cause the system clock to drift towards the VCO’s minimum

frequency, fSCM. As soon as the external clock is available again, the system

clock ramps up to its PLL target frequency. If the MCU is running on an

external clock, any loss of clock will cause the system to go static.

23.4.4

Low Power Options

This section summarizes the low power options available in the CRG.

23.4.4.1

Run Mode

This is the standard mode, all components of the system are clocked.

23.4.4.2

Doze Mode

Writing to the Doze bit puts the system in a low power consumption stand-by mode further controlled by

the CLKSEL register settings. This provides enhanced granularity in reducing the level of power

consumption. Table 23-10 lists the individual configuration bits and the parts of the MCU that are affected

in Doze Mode.

The core requests the CRG to switch into Doze Mode by writing to the DOZE bit. The CRG then checks

whether the PLLDOZE bit is asserted (Figure 23-17). Depending on the configuration, the CRG switches

the system clock to OSCCLK by clearing the PLLSEL bit and disables the PLL.

Table 23-10. MCU Configuration During Doze Mode

PLLDOZE

RTIDOZE

SWTDOZE

PLL

stopped

–

RTI Clock

–

stopped

–

SWT Clock

–

stopped

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