MAC7200 datasheet(505/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

427

•

After turning on the PLL by setting the PLLON bit, software must wait a given time (tacq) before

entering tracking mode (ACQ = 0).

•

After entering tracking mode, software must wait a given time (tal) before selecting the PLLCLK

as the source for system and peripheral clocks (PLLSEL = 1).

23.4.2.2

System Clocks Generator

Figure 23-13. System Clocks Generator

The clock generator creates the clocks used in the MCU (see Figure 23-13). The gating condition placed

on top of the individual clock gates indicates the dependencies of different modes (DOZE, DEBUG) and

the setting of the respective configuration bits.

The CPU uses the System Clock. The peripherals and memory blocks use the Peripheral Bus Clock. Some

peripheral modules also use the Oscillator Clock. If the MCU enters Self Clock Mode (see

Section 23.4.3.2, “Self Clock Mode”) the Oscillator clock source is switched to PLLCLK running at its

OSCILLATOR

PHASE

LOCK

LOOP

EXTAL

XTAL

SYSCLK

OSCCLK

PLLCLK

CLOCK PHASE

GENERATOR

Peripheral

Clock

Monitor

PLLSEL or SCM

= Clock Gate

Gating

Condition

DOZE (RTIDOZE)

DEBUG

SCM

RTI Clock

Software Watchdog

System Clock

÷2

Oscillator Clock

DOZE

(SWTDOZE)

DEBUG

Timer Clock

Bus Clock

MAC7200 Datasheet(PDF) 505 Page - Freescale Semiconductor, Inc

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