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MAC7200 Datasheet(PDF) 508 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 508 Page - Freescale Semiconductor, Inc |
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508 / 976 page ![]() Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 430 Freescale Semiconductor NOTE Remember that in parallel to additional actions caused by Self Clock Mode or Clock Monitor Reset1 handling, the clock quality checker continues to check the OSCCLK signal. NOTE The Clock Quality Checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during Doze Mode 23.4.2.5 Software Watchdog Timer (SWT) The SWT (free running watchdog timer) allows the user to check that a program is running and sequencing properly. This watchdog timer resides on the ARM platform. However, the CRG module provides the clock for the watchdog timer. 23.4.2.6 Real Time Interrupt (RTI) The RTI (real time interrupt) is in a separate module. However, the CRG module provides a special RTI clock. This is a gated OSCCLK. 23.4.3 Operating Modes 23.4.3.1 Normal Mode The CRG block behaves as described within this specification in all normal modes. 23.4.3.2 Self Clock Mode The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due to a failure or due to long crystal start-up time, the Peripheral Bus Clock and the System Clock are derived from the VCO running at the minimum operating frequency; this mode of operation is called Self Clock Mode. This requires CME=1 and CMRD=1. If the MCU was clocked by the PLL clock prior to entering Self Clock Mode, the PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. Section 23.4.2.4, “Clock Quality Checker,” for more information on entering and leaving Self Clock Mode. NOTE In order to detect a potential clock loss, the CME bit should be always enabled (CME=1). 1. A Clock Monitor Reset will always set the CMRD bit to logical’1’ |
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