MAC7200 datasheet(504/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

426

Freescale Semiconductor

23.4.2.1.2

Acquisition and Tracking Modes

The lock detector compares the frequencies of the FEEDBACK clock and the REFERENCE clock.

Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The

circuit determines the mode of the PLL and the lock condition based on this comparison.

The PLL filter can be manually or automatically configured into one of two possible operating modes:

•

Acquisition mode

In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used

at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far from

the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG

•

Tracking mode

In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter

is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking

mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register.

The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.

In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between

acquisition and tracking modes. Automatic bandwidth control mode is also used to determine when the

PLL clock (PLLCLK) is safe to use as the source for the system and peripheral clocks. If the PLL LOCK

interrupt requests are enabled, the software can wait for an interrupt request and then check the LOCK bit.

If CPU interrupts are disabled, software can poll the LOCK bit continuously (usually during PLL start-up)

or at periodic intervals. In either case, only when the LOCK bit is set is the PLLCLK clock safe to use as

the source for the system and peripheral clocks. If the PLL is selected as the source for the system and

peripheral clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must

take appropriate action, depending on the application.

The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO=1):

•

The TRACK bit is a read-only indicator of the mode of the filter.

•

The TRACK bit is set when the VCO frequency is within a certain tolerance,

trk, and is clear when

the VCO frequency is out of a certain tolerance,

unt.

•

The LOCK bit is a read-only indicator of the locked state of the PLL.

•

The LOCK bit is set when the VCO frequency is within a certain tolerance,

Lock, and is cleared

when the VCO frequency is out of a certain tolerance,

unl.

•

CPU interrupts can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the

LOCK bit.

The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not

require an indicator of the lock condition for proper operation. Such systems typically operate well below

the maximum system frequency (fsys) and require fast start-up. The following conditions apply when in

manual mode:

•ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in

manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode.

MAC7200 Datasheet(PDF) 504 Page - Freescale Semiconductor, Inc

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