MAC7200 datasheet(502/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

424

Freescale Semiconductor

23.3.2.9

CRG BDM Control Register (BDMCTL)

This register controls the SWT (Software Watchdog Timer) and RTI clocks in BDM mode.

23.4

Functional Description

23.4.1

General

This section gives detailed information on the internal operation of the design.

23.4.2

Functional Blocks

23.4.2.1

Phase Locked Loop (PLL)

The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased

flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers

Table 23-8. SDMCTL Field Descriptions

Field

Description

7–2

Reserved, should be cleared.

DOZE

Doze control bit. This bit determines whether the CRG should transition into DOZE mode.

When the CRG receives a wakeup signal, the system will leave DOZE mode and this bit will be cleared.

0 Keep running

1 Activate DOZE sequence

Reserved, should be cleared.

Address: Base + $_08

Access: User read/write

Read: anytime

Write: RSBCK: once

76543210

RSBCK

000000

Reset

00000000

Figure 23-11. CRG BDM Control Register (BDMCTL)

Table 23-9. BDMCTL Field Descriptions

Field

Description

Reserved, should be cleared.

RSBCK

SWT and RTI stop in active BDM mode (Debug Mode) bit

0 Allows the SWT and RTI to keep running in Active BDM mode

1 Stops the SWT and RTI counters whenever the part is in Active BDM mode

5–0

Reserved, should be cleared.

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