MAC7200 datasheet(503/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

425

a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126

or 128 based on the SYNR register.

Eqn. 23-2

CAUTION

Although it is possible to choose the two parameters to set a very high clock

frequency, do not exceed the specified frequency limit for the MCU. If

(PLLSEL=1), System Clock = PLLCLK.

The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on

the difference between the output frequency and the target frequency. The PLL can change between

acquisition and tracking modes either automatically or manually.

The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency fSCM.

Figure 23-12. PLL Functional Diagram

23.4.2.1.1

PLL Operation

The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is

divided in a range of 1 to 16 (REFDV+1) to output the REFERENCE clock. The VCO output clock,

(PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in

increments of [2 x (SYNR +1)] to output the FEEDBACK clock. Figure 23-12.

The phase detector then compares the FEEDBACK clock with the REFERENCE clock. Correction pulses

are generated based on the phase difference between the two signals. The loop filter then slightly alters the

DC voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the

correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the

next subsection. The values of the external filter network and the reference frequency determine the speed

of the corrections and the stability of the PLL.

PLLCLK

OSCCLK

SYNR

REFDV

-------------------------------

REDUCED

CONSUMPTION

OSCILLATOR

EXTAL

XTAL

OSCCLK

PLLCLK

REFERENCE

PROGRAMMABLE

DIVIDER

PDET

PHASE

DETECTOR

REFDV <3:0>

LOOP

PROGRAMMABLE

DIVIDER

SYN <5:0>

CPUMP

VCO

LOCK

LOOP

FILTER

XFC

DOWN

LOCK

DETECTOR

REFERENCE

FEEDBACK

VDDPLL

VDDPLL/VSSPLL

CRYSTAL

MONITOR

VDDPLL/VSSPLL

VDD/VSS

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