MAC7200 datasheet(501/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

423

23.3.2.8

CRG DOZE Control Register (SDMCTL)

This register controls the DOZE mode transitioning.

Table 23-7. PLLCTL Field Descriptions

Field

Description

CME

Clock monitor enable bit. CME enables the clock monitor. Writeable anytime except when SCM = 1.

0 Clock monitor is disabled

1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self

Clock Mode

Note: Operating with CME=0 will not detect any loss of clock. In cases of poor clock quality, this could

cause unpredictable operation of the MCU.

PLLON

Phase lock loop on bit. PLLON turns on the PLL circuitry. In Self Clock Mode, the PLL is turned on, but

the PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1.

0 PLL is turned off

1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically

AUTO

Automatic bandwidth control bit. AUTO selects either the high bandwidth (acquisition) mode or the low

bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write

anytime except when PLLDOZE=1, because PLLDOZE sets the AUTO bit to 1.

0 Automatic Mode Control is disabled and the PLL is under software control, using the ACQ bit

1 Automatic Mode Control is enabled and the ACQ bit has no effect

ACQ

Acquisition bit. Write anytime. If AUTO=1, writing to this this bit has no effect., but reading this bit indicates

which bandwidth filter is selected

0 Low bandwidth filter is selected (Acquisition Mode)

1 High bandwidth filter is selected (Tracking Mode)

3–1

Reserved, should be cleared.

CMRD

Clock monitor reset disable bit. Normal modes: Write once. Special modes: Write anytime. CMRD cannot

be cleared while operating in Self Clock Mode (SCM=1).

0 Detection of crystal clock failure causes clock monitor reset (see Section 23.4.5.4, “Clock Monitor

Reset”)

1 Detection of crystal clock failure forces the MCU into Self Clock Mode (see Section 23.4.3.2, “Self

Clock Mode”)

Address: Base + $_07

Access: User read/write

Read: anytime

Write: anytime

6543210

000000

DOZE

Reset

00000000

Figure 23-10. CRG DOZE Control Register (SDMCTL)

MAC7200 Datasheet(PDF) 501 Page - Freescale Semiconductor, Inc

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