MAC7200 datasheet(497/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

419

23.3.2.3

CRG ARM Flag Register 1 (CTFLG)

This register provides status bits and flags.

NOTE

This flags are only valid if the POR and LVR flags are cleared after reset.

NOTE

Volatile memory may not be valid after a reset, regardless of the reset cause.

Address: Base + $_02

Access: User read/write

Read: anytime

Write: refer to each bit for individual restrictions.

76543210

ILR

JTR

SFR

CMR

EXR

WDR

Reset

00000000

Figure 23-5. CRG Flag Register 1 (CTFLG)

Table 23-3. CTFLG Field Descriptions

Field

Descriptions

7–6

Reserved, should be cleared.

ILR

Illegal address reset flag. ILR is set to 1 when a bus abort reset occurs. This flag can be cleared only by

writing a 1. Writing a 0 has no effect.

0 Bus Abort reset has not occurred

1 Bus Abort reset has occurred

JTR

JTAG reset flag. JTR is set to 1 when a JTAG reset occurs. This flag can be cleared only by writing a 1.

Writing a 0 has no effect.

0 JTAG reset has not occurred

1 JTAG reset has occurred

SFR

Software reset flag. SFR is set to 1 when a software reset occurs. This flag can be cleared only by writing

a 1. Writing a 0 has no effect.

0 Software reset has not occurred

1 Software reset has occurred

CMR

Clock monitor reset flag. CMR is set to 1 when a clock monitor reset occurs. This flag can be cleared only

by writing a 1. Writing a 0 has no effect.

0 Clock Monitor reset has not occurred

1 Clock Monitor reset has occurred

EXR

External reset flag. EXR is set to 1 when an external reset occurs. This flag can be cleared only by writing

a 1. Writing a 0 has no effect.

0 External reset has not occurred

1 External reset has occurred

WDR

Software Watchdog Timer (SWT) Reset Flag. WDR is set to 1 when an SWT reset occurs. This flag can

only be cleared by writing a 1. Writing a 0 has no effect. This bit will not be valid if the Voltage Regulator

is bypassed.

0 SWT reset has not occurred

1 SWT reset has occurred

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