MAC7200 datasheet(495/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

417

23.3

Memory Map and Register Definition

This section provides a detailed description of all registers accessible in the CRG.

23.3.1

Memory Map

Figure 23-2 gives an overview of all CRG registers.

NOTE

is defined at the MCU level and the Address Offset is defined at the module

level.

23.3.2

This section describes, in address order, all the CRG registers and their individual bits.

23.3.2.1

CRG Synthesizer Register (SYNR)

The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop

divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency

by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (fSCM).

Eqn. 23-1

NOTE

If PLL is selected (PLLSEL=1), System Clock = PLLCLK

System Clock must not exceed the maximum operating system frequency.

Table 23-2. CRG Memory Map

Address

Use

Access

Base + $_00

CRG Synthesizer Register (SYNR)

R/W

Base + $_01

CRG Reference Divider Register (REFDV)

R/W

Base + $_02

CRG Flag Register 1 (CTFLG)

R/W

Base + $_03

CRG Flag Register 2 (CRGFLG)

R/W

Base + $_04

CRG Interrupt Enable Register (CRGINT)

R/W

Base + $_05

CRG Clock Select Register (CLKSEL)

R/W

Base + $_06

CRG PLL Control Register (PLLCTL)

R/W

Base + $_07

CRG STOP/Doze Control Register (SDMCTL)

R/W

Base + $_08

CRG BDM Control Register (BDMCTL)

R/W

Base + $_09- $_0F

Reserved

PLLCLK

OSCCLK

SYNR + 1

REFDV + 1

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