MAC7200 datasheet(493/976 Pages) FREESCALE

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External Signal Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

415

— User selectable disabling of clocks during Doze Mode for reduced power consumption

•

System Reset generation from the following possible sources:

— Power on reset

— Low voltage reset — this will assert if any of the Low Voltage Reset modules detect a voltage

below their set point)

—SWT reset

— Loss of clock reset

— External pin reset

23.1.4

Modes of Operation

This subsection lists and briefly describes all operating modes supported by the CRG.

•

Run Mode

All functional parts of the CRG are running during normal Run Mode.

•

Doze Mode

This mode allows to disable the system and peripheral clocks depending on the configuration of

the individual bits in the CLKSEL register.

•

Self Clock Mode

Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME) and the Clock Monitor

Reset Disable (CMRD) are both asserted and the clock monitor in the oscillator block detects a loss

of clock. As soon as Self Clock Mode is entered, the CRG starts to perform a clock quality check.

Self Clock Mode remains active until the clock quality check indicates that the required quality of

the incoming clock signal is met (frequency above hysteresis level). Self Clock Mode should be

used for safety purposes only. It provides reduced functionality to the MCU in case where a loss of

clock is causing severe system conditions.

23.2

External Signal Description

Table 23-1 lists and describes the signals that connect off chip.

Table 23-1. Signal Properties

Name

I/O Type

Function

VDDPLL

Input

Operating Voltage

VSSPLL

Input

Ground

XFC

Output/Input

External Loop Filter

RESET

Output/Input

Reset Input/Output

CLKOUT/XCLKS

Output/Input

Pierce / Square Wave Mode Selection

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