MAC7200 datasheet(491/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

413

Chapter 23

Clock and Reset Generator (CRG)

23.1

Introduction

This chapter describes the function of the Clocks and Reset Generator (CRG).

23.1.1

CRG Overview

The CRG module is used to provide the clocks for the MCU, to control its Reset operation and low power

operating modes. Included in the module is the PLL, the Clock Generator and the Reset Generator.

The module provides the clock for the Real Time Interrupt counter contained within the PIT, the clock for

the Software Watchdog Timer in the platform, the main system clock for the core and the clock used for

the peripherals and the Flash memory, which runs at half the speed of the System clock. For more

information on the clocks used throughout the MCU refer to Chapter 5, “System Clock Description”. All

memory mapped configuration for the PLL is in the CRG module.

The CRG is also used to control entry into the low power operating modes of the device, as well as the

features of the device which continue to operate during low power modes. Doze mode is entered by writing

to the Doze Control register in the CRG, while a write to the Clock Select Register will control whether

the PLL, the Real Time Interrupt (RTI) and the Software Watchdog Timer (SWT) clocks are disabled in

Doze mode.

The module provides a Crystal Monitor which detects the presence of the oscillator clock. If the oscillator

clock is not present within a defined time, determined by the Crystal Monitor time out period, the module

will either generate a Reset, or initiate the PLL Self Clock mode. In Self Clock mode the PLL will generate

its own clock based on the minimum VCO frequency. This can be used to clock the device in order to

continue some basic operation in the absence of an external clock.

The Clock Quality Checker (CQC) is included in the CRG and provides a more accurate check of the

oscillator output clock. The CQC is run following events such as Power On Reset or wake-up from STOP

mode, and counts the number of clocks over a defined time window. Failure of the Clock Quality Checker

can be used to initiate Self Clocking mode or a Crystal Monitor Reset event.

The CRG module provides information in the form of Flags to help identify the source of a Reset event

(see also Chapter 6, “Resets”).

23.1.2

CRG Block Diagram

Figure 23-1 shows a block diagram of the CRG.

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