MAC7200 datasheet(494/976 Pages) FREESCALE

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External Signal Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

416

Freescale Semiconductor

23.2.1

Detailed Signal Descriptions

23.2.1.1

VDDPLL, VSSPLL

These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This

allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required,

VDDPLL and VSSPLL must be connected properly.

23.2.1.2

XFC

A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter

to eliminate the VCO input ripple. The value of the external filter network and the reference frequency

determines the speed of the corrections and the stability of the PLL. Refer to device specification for

calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied

to VDDPLL.

Figure 23-2. PLL Loop Filter Connections

If the XFC pin is shorted to 3.3V, then the VCO will synthesize the lowest possible frequency. Since the

minimum VCO locking frequency is 30 MHz, it is expected that this situation would result in the PLL not

locking, and thus generating a software detectable condition. Because the Self Clock mode is specified as

2-5.5MHz, the device should continue to operate in Self Clock Mode, with software running and able to

detect this condition.

23.2.1.3

RESET

RESET is an active low bidirectional reset pin. As an input, it initializes the MCU asynchronously to a

known start-up state. As an open-drain output, it indicates that a system reset (internal to MCU) has been

triggered.

23.2.1.4

CLKOUT/XCLKS

After reset, CLKOUT provides the reference clock for both the GPIO and FlexBus interfaces. On the

xM84D maskset, it is driven from the Peripheral Bus Clock.

XCLKS decides between Pierce (XCLKS = 1) and Square Wave (XCLKS = 0) mode. This pin is sampled

during reset.

MCU

XFC

VDDPLL

MAC7200 Datasheet(PDF) 494 Page - Freescale Semiconductor, Inc