MAC7200 datasheet(498/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

420

Freescale Semiconductor

23.3.2.4

CRG Flags Register 2 (CRGFLG)

This register provides CRG status bits and flags.

Address: Base + $_03

Access: User read/write

Read: anytime

Write: refer to each bit for individual restrictions

76543210

PORF

LVRF

LOCKIF

LOCK

TRACK

SCMIF

SCM

Reset

00000

1 PORF is set to 1 when a power on reset occurs. Unaffected by system reset.

2 LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.

Figure 23-6. CRG Flag Register 2 (CRGFLG)

Table 23-4. CRGFLG Field Descriptions

Field

Description

Reserved, should be cleared.

PORF

Power on reset flag. PORF is set to 1 when a power on reset occurs. This flag can be cleared only by

writing a 1. Writing a 0 has no effect.

0 Power on reset has not occurred

1 Power on reset has occurred

Note: In order for the other reset source flags to be valid, this flag must be cleared after reset.

LVRF

Low voltage reset flag. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by

writing a 1. Writing a 0 has no effect. This bit will not be valid if the Voltage Regulator is bypassed.

0 Low voltage reset has not occurred

1 Low voltage reset has occurred

Note: In order for the other reset source flags to be valid, this flag must be cleared after reset.

LOCKIF

PLL lock interrupt flag. LOCKIF is set to 1 when the LOCK status bit changes. This flag can only be

cleared by writing a 1. Writing a 0 has no effect. If enabled (LOCKIE=1), LOCKIF causes an interrupt

request.

0 No change in LOCK bit

1 LOCK bit has changed

LOCK

Lock status bit. LOCK reflects the current state of PLL lock condition. This bit is cleared in Self Clock

Mode. Writes have no effect.

0 PLL VCO is not within the desired tolerance of the target frequency

1 PLL VCO is within the desired tolerance of the target frequency

TRACK

Track status bit. TRACK reflects the current state of the PLL track condition. This bit is cleared in Self

Clock Mode. Writes have no effect.

0 Acquisition mode status

1 Tracking mode status

MAC7200 Datasheet(PDF) 498 Page - Freescale Semiconductor, Inc

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