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MAC7200 Datasheet(PDF) 506 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 506 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
428
Freescale Semiconductor
minimum frequency, fSCM. The System Clock is twice the Peripheral Bus Clock as shown in Figure 23-14.
Note that a CPU cycle corresponds to one Peripheral Bus Clock.
Figure 23-14. System Clock and Peripheral Bus Clock Relationship
PLL clock mode is selected with the PLLSEL bit in the CLKSEL register. When selected, the PLL output
clock drives SYSCLK for the main system, including the CPU and peripherals. The PLL cannot be turned
off by clearing the PLLON bit if the PLL clock is selected. When PLLSEL is changed, it takes a maximum
of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and
CPU activity ceases.
23.4.2.3
Clock Monitor (CM)
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The CRG then asserts self clock mode or generates a system reset
depending on the state of the CMRD bit. If the clock monitor is disabled or the presence of clocks is
detected, no failure is indicated by the oscillator block. The clock monitor function is enabled/disabled by
the CME control bit.
23.4.2.4
Clock Quality Checker
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.
A clock quality check is triggered by any of the following events:
•
Power on reset (POR)
•
Low voltage reset (LVR)
•
Clock Monitor fail indication (CM fail)
A time window of 50000 VCO clock cycles1 is called check window.
A number greater than or equal to 4096 rising OSCCLK edges within a check window is called osc ok.
Note that osc ok immediately terminates the current check window. See Figure 23-15 as an example.
1.
VCO clock cycles are generated by the PLL when running at minimum frequency fSCM.
System Clock:
Peripheral Bus Clock
Memory Clock



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