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MAC7200 Datasheet(PDF) 511 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 511 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
433
completing the reset sequence, processing begins by fetching the normal reset vector. Doze Mode is exited
and the MCU is in Run Mode again.
If the clock monitor is enabled (CME=1) the MCU is able to exit Doze-Mode when loss of
oscillator/external clock is detected by a clock monitor fail. If the CMRD bit is not asserted, the CRG
generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same
compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the
CMRD bit is asserted, the CRG generates an SCM interrupt if enabled (SCMIE=1). After generating the
interrupt, the CRG enters Self-Clock Mode and starts the clock quality checker (Section 23.4.2.4, “Clock
Quality Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by
SCMIE=0, the SCMIF flag will be asserted and clock quality checks will be performed, but the MCU will
not wake-up from Doze-Mode.
If any other interrupt source (e.g. RTI) triggers the exit from Doze Mode, the MCU immediately continues
with normal operation. If the PLL has been powered-down during Doze-Mode, the PLLSEL bit is cleared
and the MCU runs on OSCCLK after leaving Doze-Mode. The software must manually set the PLLSEL
bit again, in order to switch system and peripheral clocks to the PLLCLK.
If Doze Mode is entered from Self-Clock Mode, the CRG will continue to check the clock quality until the
clock check is successful. The PLL and voltage regulator (VREG) will remain enabled.
Table 23-11 summarizes the outcome of a clock loss while in Doze Mode.
Table 23-11. Outcome of Clock Loss in Doze Mode
CME
CMRD
SCMIE
CRG Actions
0
X
X
Clock failure
→
No action, clock loss not detected.
1
0
X
Clock failure
→
CRG performs Clock Monitor Reset immediately



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