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MAC7200 Datasheet(PDF) 515 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 515 Page - Freescale Semiconductor, Inc |
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515 / 976 page ![]() Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 437 Figure 23-18. RESET Timing The debug block reset is asserted together with the internal reset, but will not be extended by the external RESET pin. In addition, the debug block reset will be asserted only if the reset sequence was initiated by a power-on or low-voltage indication. The Flash_POR signal is asserted on POR or LVR conditions. It will be synchronously released after 128+n clock cycles. The reset sequence will be extended by m cycles till the Flash block acknowledges that it has completed its reset. The number m will depend on the external crystal as well as on the characteristics of the Flash. It will vary for each device. This enables the user to activate the debugger in two ways: either by holding the reset input asserted while the debugger is being activated or by setting up the debugger after a power-on reset, then applying an additional reset that will not affect the debug logic (i.e. not a power-on reset). Note that the Power-On reset sequence is not complete until least 8 cycles after the CRG releases the RESET line. If another external reset occurs before the 8 cycles have expired, that new reset will also be treated as a Power-On-Reset, so DEBUG_RESET will be asserted again. with n being min 3 / max 6 cycles depending on internal synchronization delay RESET / SYSCLK SYS_RST CRG drives RESET RESET pin released only on power-on ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( possibly SYSCLK not running 128 + n cycles 128 cycles 64 cycles possibly RESET driven low externally pin low min 8 cycles to complete Power-On reset sequence m cycles ) ( ) ( ) ( ) ( wait until Flash reset is complete DEBUG_RST FLASH_POR EARLY_RST ) ( ) ( ) ( ) ( ) ( ) ( |
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