MAC7200 datasheet(519/976 Pages) FREESCALE

519 / 976 page

CRG Application Usage

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

441

— Removed the FSTWKP, PRE and PWE bits from the PLLCTL register

— Removed the STOP bit from the SDMCTL register

•

Renamed the SCME bit in the PLLCTL register to CMRD (no functionality change)

•

Removed the DOZE_ROA bit from the CLKSEL register (The oscillator does not support this

feature)

•

Changed the latching of the oscillator mode (XCLKS)

— The oscillator mode (XCLKS) is latched only during a power-on reset and during a reset while

a loss of clock has occurred. It is no longer latched during a normal system reset.

•

XFC changed from 2.5V to 3.3V signal

•

Changed max PLL frequency from 40MHz to 70MHz. Minimum VCO lock changed to 30MHz

•

PLL Loop filter calculations in the documentation may be revised slightly

23.7

CRG Application Usage

23.7.1

Enabling the CRG and PLL

It is not necessary to enable the CRG before it can be used.

Note that the PLL is bypassed when the device comes out of reset. It is the responsibility of the boot code

to configure and enable the PLL. This should be done as early in the boot process as possible (after the

PLL has locked) in order to minimize the time required for boot.

23.7.2

Crystal Monitor

The MAC72xx provides an on-chip Crystal Monitor that detects a loss of Oscillator Clock. If no OSCCLK

edges are detected within a certain time, referred to as the Crystal Monitor Timeout, the Crystal Monitor

within the oscillator block generates a Crystal Monitor fail event. Depending on the state of the CMRD

bit in the PLLCTL register and the SCMIE bit in the CRGINT register, one of several events can occur

when the Crystal Monitor detects a loss of Oscillator Clock.

•

The CRG generates a Crystal Monitor Reset, which causes a System Reset. The CMR reset status

bit in the CTFLG register is set, and after the reset sequence has completed, may be read to

determine that a Crystal Monitor Reset has occurred. (CMRD = 0)

•

The system enters Self Clock Mode, the CRG raises an SCM interrupt, and the SCMIF and SCM

bits in the CRGFLG register are set. (CMRD = 1, SCMIE = 1)

•

The system enters Self Clock Mode and the SCMIF and SCM bits in the CRGFLG register are

set.(CMRD = 1, SCMIE = 0)

If the CME bit in the PLLCTL register is cleared, then the Crystal Monitor is disabled, and the loss of

Oscillator Clock becomes essentially undetectable in software. For this reason, it is highly recommended

to enable this functionality. Note that the terms “Crystal Monitor” and “Clock Monitor” are used

interchangeably in the MAC72xx documentation.

MAC7200 Datasheet(PDF) 519 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 519 Page - Freescale Semiconductor, Inc

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