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MAC7200 Datasheet(PDF) 516 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 516 Page - Freescale Semiconductor, Inc |
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516 / 976 page ![]() Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 438 Freescale Semiconductor 23.4.5.3 JTAG Reset The DEBUG_RESET line can also be asserted via a JTAG command (see Figure 23-19). This causes a much shorter reset sequence, solely for the DEBUG_RESET - other parts of the device are not affected. NOTE The JTAG reset sequence can not be mixed with another reset sequence. Figure 23-19. RESET Timing controlled by JTAG 23.4.5.4 Clock Monitor Reset The CRG generates a Clock Monitor Reset when all of the following conditions are true: • Clock monitor is enabled (CME=1) • Loss of clock is detected • Self-Clock Mode is disabled (CMRD=0) The reset event asynchronously forces the configuration registers to their default settings (see Section 23.3, “Memory Map and Register Definition).” The CME and the CMRD are reset to logical ‘1’ (which doesn’t change the state of the CME bit, because it has already been set). As a consequence, the CRG immediately enters Self Clock Mode and starts its internal reset sequence. In parallel, the clock quality check starts. As soon as the clock quality check indicates a valid Oscillator Clock, the CRG switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running in parallel with the reset generator, the CRG may leave Self Clock Mode while still completing the internal reset sequence. When the reset sequence is finished, the CRG checks the internally latched state of the clock monitor fail circuit. 23.4.5.5 Software Watchdog Timer (SWT) Reset The CRG will generate a reset if the Watchdog reset is indicated by the ARM platform. 23.4.5.6 Power On Reset, Low Voltage Reset The on-chip voltage regulators detect when VDDs to the MCU have reached a certain level and assert a power on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered, Apply JTAG command 16 +n cycles DEBUG_RESET FLASH_RESET RESET / SYS_RES |
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