MAC7200 datasheet(513/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

435

23.4.5

Resets

23.4.5.1

General

This section describes how to reset the CRG and how the CRG controls the reset of the MCU. It explains

all special reset requirements. Since the reset generator for the MCU is part of the CRG, this section also

describes all automatic actions that occur during or as a result of individual reset conditions. The reset

values of registers and signals are provided in Section 23.3, “Memory Map and Register Definition.” All

reset sources are listed in Table 23-13. Refer to the MCU specification for related vector addresses and

priorities.

23.4.5.2

Description of Reset Operation

The reset sequence is initiated by any of the following events:

•

Low level is detected at the RESET pin (External Reset)

Clock failure

→

– VREG enabled

– PLL enabled

– SCM activated

– Start Clock Quality Check

– SCMIF set

SCMIF generates Self Clock Mode wakeup interrupt

– Exit Doze Mode in SCM using PLL clock (fSCM) as system clock

– Continue to perform a additional Clock Quality Checks until OSCCLK is ok again

Table 23-12. Entering CRG Modes

Mode

Sequence

Doze

– Doze register bit in the CRG is written

– CRG indicates Doze mode

– The system will turn off peripherals’ clocks according to their DOZE bits

– RTI and SWT clocks will be turned off according to their DOZE bits

Table 23-13. Reset Summary

Reset Source

Local Enable

Power on Reset

None

Low Voltage Reset

None

External Reset

None

Clock Monitor Reset

PLLCTL (CME=1, CMRD=0)

SWT Watchdog Reset

None

Table 23-11. Outcome of Clock Loss in Doze Mode (Continued)

CME

CMRD

SCMIE

CRG Actions

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