MAC7200 datasheet(539/976 Pages) FREESCALE

539 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

461

Chapter 26

Periodic Interrupt Timer (PIT_RTI)

26.1

Introduction

This section describes the function of the Periodic Interrupt Timer block (PIT_RTI) on the MAC7200. The

PIT is an array of timers that can be used to raise interrupts and trigger DMA channels. It also provides a

dedicated Real Time Interrupt Timer (RTI), which runs on a separate clock and can be used for system

wakeup.

26.1.1

Overview

The Periodic Interrupt Timer provides ten programmable 32-bit timers offering a range of functions plus

one programmable 24-bit Real Timer Interrupt (RTI). Once reaching zero, a trigger can be generated and

the counter is reloaded with the start value and continues to be decremented. If required, the value of each

of the timers down count can be read by software at any time.

The PIT has one Real Time Interrupt (RTI), four general purpose timers, four dedicated timers used to

trigger DMA transfers and two timers used to trigger ATD conversions.

PIT 0 is used to provide the RTI and can generate an interrupt which may also be inhibited. The four

general purpose timers, PIT 1 to PIT4 can be used to generate interrupts or to trigger DMA channels 4 to

7. PIT 5 to PIT 8 are used to trigger DMA channels 0 to 3. PIT 9 and 10 are used for the ATD triggers

SYSTRIG0 and SYSTRIG1 respectively. Note that PIT4 and the RTI share the same interrupt vector.

Therefore, to use just the RTI as an interrupt, you must disable the interrupt for PIT4. Conversely, to use

just PIT4 as an interrupt source, you must disable the interrupt for the RTI.

All of the PITs take their clock from the system clock frequency FSYS with the exception of the RTI which

uses the oscillator clock as its source. This allows the RTI to continue operating while in low power modes.

The PIT module can be independently disabled by writing to the MDIS bit in the modules PITCTRL

This will disable PIT 1 to 10, but will allow the RTI to continue operating and for most of the module

registers to remain accessible by the core across the peripheral bus. The MDIS bit is intended to be used

when the module is not required in the application. By default the PIT is disabled after reset (MDIS=1),

so, prior to use, the MDIS bit must be cleared. Alternatively, each timer may be independently disabled.

26.1.2

Block Diagram

Figure 26-1 shows the PIT block diagram.

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