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MAC7200 Datasheet(PDF) 561 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 561 Page - Freescale Semiconductor, Inc |
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561 / 976 page ![]() Memory Map and Register Definition MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 483 27.3 Memory Map and Register Definition This section provides a detailed description of all memory-mapped registers in the DMA Mux. Table 27-2 shows the memory map for the DMA Mux. Note that all addresses are offsets; the absolute address may be computed by adding the specified offset to the base address of the DMA Mux. All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, CHCONFIG0 through CHCONFIG4 are accessible by a 32-bit READ/WRITE to address ‘Base + 0x00’, but performing a 32-bit access to address ‘Base + 0x01’ is illegal. 27.3.1 Register Descriptions The following memory-mapped registers are available in the DMA Channel Mux. 27.3.1.1 Channel Configuration Registers Each of the total of 16 DMA channels can be independently enabled/disabled and associated with 1 of the 30 total DMA sources in the system. Table 27-2. Module Memory Map Address Use Access Base + $0x00 Channel #0 Configuration (CHCONFIG0) R/W Base + $0x01 Channel #1 Configuration (CHCONFIG1) R/W Base + $0x02 Channel #2 Configuration (CHCONFIG2) R/W Base + $0x03 Channel #3 Configuration (CHCONFIG3) R/W Base + $0x04 Channel #4 Configuration (CHCONFIG4) R/W Base + $0x05 Channel #5 Configuration (CHCONFIG5) R/W Base + $0x06 Channel #6 Configuration (CHCONFIG6) R/W Base + $0x07 Channel #7 Configuration (CHCONFIG7) R/W Base + $0x08 Channel #8 Configuration (CHCONFIG8) R/W Base + $0x09 Channel #9 Configuration (CHCONFIG9) R/W Base + $0x0A Channel #10 Configuration (CHCONFIG10) R/W Base + $0x0B Channel #11 Configuration (CHCONFIG11) R/W Base + $0x0C Channel #12 Configuration (CHCONFIG12) R/W Base + $0x0D Channel #13 Configuration (CHCONFIG13) R/W Base + $0x0E Channel #14 Configuration (CHCONFIG14) R/W Base + $0x0F Channel #15 Configuration (CHCONFIG15) R/W |
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