MAC7200 datasheet(706/976 Pages) FREESCALE

706 / 976 page

eSCI Protocol

MAC7200 Microcontroller Family Reference Manual, Rev. 2

628

Freescale Semiconductor

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Detection of Bit Errors, Physical Bus Errors and Checksum Errors

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All status bit can generate maskable interrupts

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Application layer CRC support

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Programmable CRC polynom

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Double Stop Flag insertion after Bit Errors

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Detection and generation of wakeup characters

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Programmable wakeup delimiter time

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Programmable slave timeout

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Can be configured to include header bits in checksum

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LIN DMA interface

Please refer to the LIN Specification Package for details about the LIN protocol.

31.2.2

Modes of Operation

The SCI functions the same in normal, special, and emulation modes. It also has a low power Doze mode.

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Run Mode

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Doze Mode

The eSCI delays the system going into stop mode, until it has completely transmitted the current TX byte,

or completely received the current RX byte. In LIN mode it will complete any frames which don’t require

further processor intervention (e.g. transmission of a checksum byte).

31.3

eSCI Protocol

31.3.1

LIN Protocol Summary

The LIN bus has the following characteristics:

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2-wire, full duplex bus (RXD + TXD)

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Synchronous (the clock is derived from the data stream)

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Single-master, multi-slave

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Transmit “monitoring”. The LIN master is responsible for checking that the transmitted data is the

same as the data on the bus

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Bit rate from 1 kb/s to 19.2 kb/s, with recommended rates of 2400 bps, 9600 bps and 19200 bps.

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8N1 byte encoding, LSB first (1 Start + 8 Data + 1 stop bit). In this sense, a “byte” is 10 bits (as

measured by the bit time/slice).

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Payload is delivered in a Message Frame, which consists of:

MAC7200 Datasheet(PDF) 706 Page - Freescale Semiconductor, Inc

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